In recent years, integration of semiconductor chips has progressed, and circuit blocks that realize many more functions have been integrated into a single chip. When a plurality of circuit blocks are integrated within a single chip, wirings used to exchange signals are connected to each circuit block.
When digital data or a digital control signal is supplied to each circuit block within a semiconductor chip, wirings to each circuit block are required, in accordance with the number of the circuit blocks and in accordance with the number of bits of targeted digital data, etc.
FIG. 1 is a schematic diagram showing the structure of a conventional integrated circuit which a plurality of circuit blocks are integrated within a single semiconductor chip. In FIG. 1, “1” denotes a decoding circuit that is comprised by a serial interface circuit, and “2” to “7” denotes a plurality of circuit blocks. The semiconductor chip 100 integrates one decoding circuit 1 and a plurality of circuit blocks 2 to 7.
A plurality of signal lines 8, including address lines and data lines, are connected to an input terminal of the decoding circuit 1. The decoding circuit 1 decodes the address signal with a few bits inputted from the address line, and outputs the digital data inputted from the data line, in an amount equivalent to the number of addresses after decoding.
Therefore, the signal lines 20 including a number thereof equivalent to (number of addresses after decoding)×(number of bits of digital data) are connected to an output terminal of the decoding circuit 1. For instance, when the address line of the signal lines 8 is 4 bits and the data line is 16 bits, the number of addresses after decoding is 16. Thus, the signal lines 20 of a number obtained from 16×16 (=256) are connected to the output terminal of the decoding circuit 1. And such signal lines 20 are wired to each circuit block 2 to 7.
However, regarding the conventional integrated circuit shown in the FIG. 1, 256 wirings are connected to each circuit block 2 to 7, arranged in a scattered manner within the semiconductor chip 100, from the decoding circuit 1. Thus, this causes a problem in that an extremely large number of wirings are routed over the semiconductor chip 100, and the chip area increased in accordance with that amount.
Also, since many wirings are routed over the semiconductor chip 100, noise is caused on the adjacent wirings when a high-speed signal is transmitted. This is also a problem where so-called “crosstalk” noise is caused in many places. Thus, there has been an additional problem where designing a suitable chip layout is very difficult and the efficiency of the development of integrated circuits declined.
The purpose of the present invention is to resolve such problems, to reduce the number of wirings routed over the chip in a semiconductor chip that integrates a plurality of circuit blocks, and to realize miniaturization of chip size, reduction of crosstalk noise, and facilitation of layout.